diff --git a/scope.py b/scope.py
index 9e85a29..7bbc139 100755
--- a/scope.py
+++ b/scope.py
@@ -3,6 +3,7 @@
 import argparse
 import asyncio
 import logging
+import math
 import os
 import struct
 
@@ -33,10 +34,6 @@ class Scope(vm.VirtualMachine):
         await scope.setup()
         return scope
 
-    @staticmethod
-    def _analog_map_func(ks, low, high):
-        return ks[0] + ks[1]*low + ks[2]*high
-
     async def setup(self):
         Log.info("Resetting scope")
         await self.reset()
@@ -173,17 +170,17 @@ class Scope(vm.VirtualMachine):
         for dump_channel, channel in enumerate(sorted(channels)):
             async with self.transaction():
                 await self.set_registers(SampleAddress=(address - nsamples) * nsamples_multiplier % buffer_width,
-                                         DumpMode=clock_mode.DumpMode, DumpChan=dump_channel,
-                                         DumpCount=nsamples, DumpRepeat=1, DumpSend=1, DumpSkip=0)
+                                         DumpMode=vm.DumpMode.Native if clock_mode.sample_width == 2 else vm.DumpMode.Raw, 
+                                         DumpChan=dump_channel, DumpCount=nsamples, DumpRepeat=1, DumpSend=1, DumpSkip=0)
                 await self.issue_program_spock_registers()
                 await self.issue_analog_dump_binary()
             data = await self._reader.readexactly(nsamples * clock_mode.sample_width)
             if clock_mode.sample_width == 2:
+                data = struct.unpack('>{}h'.format(nsamples), data)
                 if raw:
-                    trace = [(value / 65536 + 0.5) for value in struct.unpack('>{}h'.format(nsamples), data)]
+                    trace = [(value / 65536 + 0.5) for value in data]
                 else:
-                    trace = [(value / 65536 + 0.5) * (high - low) + low + self.analog_offsets[channel]
-                             for value in struct.unpack('>{}h'.format(nsamples), data)]
+                    trace = [(value / 65536 + 0.5) * (high - low) + low + self.analog_offsets[channel] for value in data]
             else:
                 if raw:
                     trace = [value / 256 for value in data]
@@ -197,7 +194,7 @@ class Scope(vm.VirtualMachine):
         if vpp is None:
             vpp = self.awg_maximum_voltage
         possible_params = []
-        max_clock = int(round(1 / frequency / min_samples / self.awg_clock_period, 0))
+        max_clock = int(math.floor(1 / frequency / min_samples / self.awg_clock_period))
         for clock in range(self.awg_minimum_clock, max_clock+1):
             width = 1 / frequency / (clock * self.awg_clock_period)
             if width <= self.awg_sample_buffer_size:
@@ -221,8 +218,8 @@ class Scope(vm.VirtualMachine):
                     raise ValueError("Wavetable data must be {} samples".format(self.awg_wavetable_size))
                 await self.set_registers(Cmd=0, Mode=1, Address=0, Size=1)
                 await self.wavetable_write_bytes(wavetable)
-            await self.set_registers(Cmd=0, Mode=0, Level=vpp/self.awg_maximum_voltage,
-                                     Offset=2*offset/self.awg_maximum_voltage,
+            await self.set_registers(Cmd=0, Mode=0, Level=vpp / self.awg_maximum_voltage,
+                                     Offset=offset / self.awg_maximum_voltage,
                                      Ratio=nwaves * self.awg_wavetable_size / size,
                                      Index=0, Address=0, Size=size)
             await self.issue_translate_wavetable()
diff --git a/vm.py b/vm.py
index 684e1ed..8037cae 100644
--- a/vm.py
+++ b/vm.py
@@ -49,7 +49,7 @@ Registers = {
     "Clock": (0x50, 'U16', "Sample (clock) period (ticks)"),
     "Modulo": (0x52, 'U16', "Modulo Size (generic)"),
     "Level": (0x54, 'U0.16', "Output (analog) attenuation (unsigned)"),
-    "Offset": (0x56, 'S1.15', "Output (analog) offset (signed)"),
+    "Offset": (0x56, 'S0.16', "Output (analog) offset (signed)"),
     "Mask": (0x58, 'U16', "Translate source modulo mask"),
     "Ratio": (0x5a, 'U16.16', "Translate command ratio (phase step)"),
     "Mark": (0x5e, 'U16', "Mark count/phase (ticks/step)"),
@@ -138,17 +138,17 @@ class KitchenSinkB(IntEnum):
     WaveformGeneratorEnable  = 0x40
 
 ClockMode = namedtuple('ClockMode', ('clock_low', 'clock_high', 'clock_max', 'dual', 'sample_width',
-                                     'TraceMode', 'BufferMode', 'DumpMode'))
+                                     'TraceMode', 'BufferMode'))
 
 ClockModes = [
-    ClockMode(40, 65536, None, False, 2, TraceMode.Macro,          BufferMode.Macro,     DumpMode.Native),
-    ClockMode(40, 65536, None, True,  2, TraceMode.MacroChop,      BufferMode.MacroChop, DumpMode.Native),
-    ClockMode(15,    40, None, False, 1, TraceMode.Analog,         BufferMode.Single,    DumpMode.Raw),
-    ClockMode(13,    40, None, True,  1, TraceMode.AnalogChop,     BufferMode.Chop,      DumpMode.Raw),
-    ClockMode( 8,    14, None, False, 1, TraceMode.AnalogFast,     BufferMode.Single,    DumpMode.Raw),
-    ClockMode( 8,    40, None, True,  1, TraceMode.AnalogFastChop, BufferMode.Chop,      DumpMode.Raw),
-    ClockMode( 2,     8, 5,    False, 1, TraceMode.AnalogShot,     BufferMode.Single,    DumpMode.Raw),
-    ClockMode( 4,     8, 5,    True,  1, TraceMode.AnalogShotChop, BufferMode.Chop,      DumpMode.Raw),
+    ClockMode(40, 65536, None, False, 2, TraceMode.Macro,          BufferMode.Macro),
+    ClockMode(40, 65536, None, True,  2, TraceMode.MacroChop,      BufferMode.MacroChop),
+    ClockMode(15,    40, None, False, 1, TraceMode.Analog,         BufferMode.Single),
+    ClockMode(13,    40, None, True,  1, TraceMode.AnalogChop,     BufferMode.Chop),
+    ClockMode( 8,    14, None, False, 1, TraceMode.AnalogFast,     BufferMode.Single),
+    ClockMode( 8,    40, None, True,  1, TraceMode.AnalogFastChop, BufferMode.Chop),
+    ClockMode( 2,     8, 5,    False, 1, TraceMode.AnalogShot,     BufferMode.Single),
+    ClockMode( 4,     8, 5,    True,  1, TraceMode.AnalogShotChop, BufferMode.Chop),
 ]
 
 def encode(value, dtype):