Tidier constants

scope.py

@@ -1,10 +1,11 @@
 
 import asyncio
 from streams import SerialStream
-from vm import VirtualMachine
+
+import vm
 
 
-class Scope(VirtualMachine):
+class Scope(vm.VirtualMachine):
 
     @classmethod
     async def connect(cls, stream=None):
@@ -47,7 +48,7 @@ class Scope(VirtualMachine):
             raise ValueError("Unable to find appropriate solution to required frequency")
         size, nwaves, clock, actualf = best_params
         async with self.transaction():
-            await self.set_registers(vrKitchenSinkB=VirtualMachine.KITCHENSINKB_WAVEFORM_GENERATOR_ENABLE)
+            await self.set_registers(vrKitchenSinkB=vm.KitchenSinkB.WaveformGeneratorEnable)
             await self.issue_configure_device_hardware()
         await self.synthesize_wavetable(waveform, ratio)
         await self.translate_wavetable(nwaves=nwaves, size=size, level=vpp/self.awg_maximum_voltage, offset=offset/self.awg_maximum_voltage)

vm.py

@@ -1,27 +1,8 @@
 
-
 import asyncio
 import numpy as np
 import struct
 
-
-class VirtualMachine:
-
-    class Transaction:
-        def __init__(self, vm):
-            self._vm = vm
-        def append(self, cmd):
-            self._data += cmd
-        async def __aenter__(self):
-            self._data = b''
-            self._vm._transactions.append(self)
-            return self
-        async def __aexit__(self, exc_type, exc_value, traceback):
-            self._vm._transactions.pop()
-            if exc_type is None:
-                await self._vm.issue(self._data)
-            return False
-
 Registers = {
     "vrTriggerLogic": (0x05, 'U8', "Trigger Logic, one bit per channel (0 => Low, 1 => High)"),
     "vrTriggerMask": (0x06, 'U8', "Trigger Mask, one bit per channel (0 => Don’t Care, 1 => Active)"),
@@ -101,46 +82,70 @@ class VirtualMachine:
     "vcBaudHost": (0xfe, 'U16', "baud rate (host side)"),
 }
 
-    TraceModes = {
-        "tmAnalog": 0,
-        "tmAnalogFast": 4,
-        "tmAnalogShot": 11,
-        "tmMixed": 1,
-        "tmMixedFast": 5,
-        "tmMixedShot": 12,
-        "tmLogic": 14,
-        "tmLogicFast": 15,
-        "tmLogicShot": 13,
-        "tmAnalogChop": 2,
-        "tmAnalogFastChop": 6,
-        "tmAnalogShotChop": 16,
-        "tmMixedChop": 3,
-        "tmMixedFastChop": 7,
-        "tmMixedShotChop": 17,
-        "tmMacro": 18,
-        "tmMacroChop": 19,
-    }
 
-    BufferModes = {
+class TraceMode:
-        "bmSingle": 0,
+    Analog         =  0
-        "bmChop": 1,
+    AnalogFast     =  4
-        "bmDual": 2,
+    AnalogShot     = 11
-        "bmChopDual": 3,
+    Mixed          =  1
-        "bmMacro": 4,
+    MixedFast      =  5
-        "bmMacroChop": 5,
+    MixedShot      = 12
-    }
+    Logic          = 14
+    LogicFast      = 15
+    LogicShot      = 13
+    AnalogChop     =  2
+    AnalogFastChop =  6
+    AnalogShotChop = 16
+    MixedChop      =  3
+    MixedFastChop  =  7
+    MixedShotChop  = 17
+    Macro          = 18
+    MacroChop      = 19
 
-    SPOCKOPTION_TRIGGER_INVERT               = 0x40
-    SPOCKOPTION_TRIGGER_SOURCE_A             = 0x00
-    SPOCKOPTION_TRIGGER_SOURCE_B             = 0x04
-    SPOCKOPTION_TRIGGER_SWAP                 = 0x02
-    SPOCKOPTION_TRIGGER_TYPE_SAMPLED_ANALOG  = 0x00
-    SPOCKOPTION_TRIGGER_TYPE_HARDWARE        = 0x01
 
-    KITCHENSINKA_CHANNEL_A_COMPARATOR_ENABLE = 0x80
+class BufferModes:
-    KITCHENSINKA_CHANNEL_B_COMPARATOR_ENABLE = 0x40
+    Single    = 0
-    KITCHENSINKB_ANALOG_FILTER_ENABLE        = 0x80
+    Chop      = 1
-    KITCHENSINKB_WAVEFORM_GENERATOR_ENABLE   = 0x40
+    Dual      = 2
+    ChopDual  = 3
+    Macro     = 4
+    MacroChop = 5
+
+
+class SpockOptions:
+    TriggerInvert        = 0x40
+    TriggerSourceA       = 0x00
+    TriggerSourceB       = 0x04
+    TriggerSwap          = 0x02
+    TriggerSampledAnalog = 0x00
+    TriggerHardware      = 0x01
+
+
+class KitchenSinkA:
+    ChannelAComparatorEnable = 0x80
+    ChannelBComparatorEnable = 0x40
+
+class KitchenSinkB:
+    AnalogFilterEnable       = 0x80
+    WaveformGeneratorEnable  = 0x40
+
+
+class VirtualMachine:
+
+    class Transaction:
+        def __init__(self, vm):
+            self._vm = vm
+        def append(self, cmd):
+            self._data += cmd
+        async def __aenter__(self):
+            self._data = b''
+            self._vm._transactions.append(self)
+            return self
+        async def __aexit__(self, exc_type, exc_value, traceback):
+            self._vm._transactions.pop()
+            if exc_type is None:
+                await self._vm.issue(self._data)
+            return False
 
     def __init__(self, stream):
         self._stream = stream
@@ -219,8 +224,8 @@ class VirtualMachine:
     async def set_registers(self, **kwargs):
         cmd = ''
         r0 = r1 = None
-        for base, name in sorted((self.Registers[name][0], name) for name in kwargs):
+        for base, name in sorted((Registers[name][0], name) for name in kwargs):
-            base, dtype, desc = self.Registers[name]
+            base, dtype, desc = Registers[name]
             for i, byte in enumerate(self.encode(kwargs[name], dtype)):
                 if cmd:
                     cmd += 'z'
@@ -239,7 +244,7 @@ class VirtualMachine:
             await self.issue(cmd + 's')
 
     async def get_register(self, name):
-        base, dtype, desc = self.Registers[name]
+        base, dtype, desc = Registers[name]
         await self.issue('{:02x}@p'.format(base))
         values = []
         width = self.calculate_width(dtype)