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mirror of https://github.com/jonathanhogg/scopething synced 2025-07-14 11:12:09 +01:00

Tidier constants

This commit is contained in:
Jonathan Hogg
2016-10-14 12:36:31 +01:00
parent d4e6244bba
commit 5ab80ddf1d
2 changed files with 133 additions and 127 deletions

View File

@ -1,10 +1,11 @@
import asyncio
from streams import SerialStream
from vm import VirtualMachine
import vm
class Scope(VirtualMachine):
class Scope(vm.VirtualMachine):
@classmethod
async def connect(cls, stream=None):
@ -47,7 +48,7 @@ class Scope(VirtualMachine):
raise ValueError("Unable to find appropriate solution to required frequency")
size, nwaves, clock, actualf = best_params
async with self.transaction():
await self.set_registers(vrKitchenSinkB=VirtualMachine.KITCHENSINKB_WAVEFORM_GENERATOR_ENABLE)
await self.set_registers(vrKitchenSinkB=vm.KitchenSinkB.WaveformGeneratorEnable)
await self.issue_configure_device_hardware()
await self.synthesize_wavetable(waveform, ratio)
await self.translate_wavetable(nwaves=nwaves, size=size, level=vpp/self.awg_maximum_voltage, offset=offset/self.awg_maximum_voltage)

127
vm.py
View File

@ -1,28 +1,9 @@
import asyncio
import numpy as np
import struct
class VirtualMachine:
class Transaction:
def __init__(self, vm):
self._vm = vm
def append(self, cmd):
self._data += cmd
async def __aenter__(self):
self._data = b''
self._vm._transactions.append(self)
return self
async def __aexit__(self, exc_type, exc_value, traceback):
self._vm._transactions.pop()
if exc_type is None:
await self._vm.issue(self._data)
return False
Registers = {
Registers = {
"vrTriggerLogic": (0x05, 'U8', "Trigger Logic, one bit per channel (0 => Low, 1 => High)"),
"vrTriggerMask": (0x06, 'U8', "Trigger Mask, one bit per channel (0 => Dont Care, 1 => Active)"),
"vrSpockOption": (0x07, 'U8', "Spock Option Register (see bit definition table for details)"),
@ -99,48 +80,72 @@ class VirtualMachine:
"vrLedLevelGRN": (0xfb, 'U8', "Green LED Intensity (VM10 only)"),
"vrLedLevelYEL": (0xfc, 'U8', "Yellow LED Intensity (VM10 only)"),
"vcBaudHost": (0xfe, 'U16', "baud rate (host side)"),
}
}
TraceModes = {
"tmAnalog": 0,
"tmAnalogFast": 4,
"tmAnalogShot": 11,
"tmMixed": 1,
"tmMixedFast": 5,
"tmMixedShot": 12,
"tmLogic": 14,
"tmLogicFast": 15,
"tmLogicShot": 13,
"tmAnalogChop": 2,
"tmAnalogFastChop": 6,
"tmAnalogShotChop": 16,
"tmMixedChop": 3,
"tmMixedFastChop": 7,
"tmMixedShotChop": 17,
"tmMacro": 18,
"tmMacroChop": 19,
}
BufferModes = {
"bmSingle": 0,
"bmChop": 1,
"bmDual": 2,
"bmChopDual": 3,
"bmMacro": 4,
"bmMacroChop": 5,
}
class TraceMode:
Analog = 0
AnalogFast = 4
AnalogShot = 11
Mixed = 1
MixedFast = 5
MixedShot = 12
Logic = 14
LogicFast = 15
LogicShot = 13
AnalogChop = 2
AnalogFastChop = 6
AnalogShotChop = 16
MixedChop = 3
MixedFastChop = 7
MixedShotChop = 17
Macro = 18
MacroChop = 19
SPOCKOPTION_TRIGGER_INVERT = 0x40
SPOCKOPTION_TRIGGER_SOURCE_A = 0x00
SPOCKOPTION_TRIGGER_SOURCE_B = 0x04
SPOCKOPTION_TRIGGER_SWAP = 0x02
SPOCKOPTION_TRIGGER_TYPE_SAMPLED_ANALOG = 0x00
SPOCKOPTION_TRIGGER_TYPE_HARDWARE = 0x01
KITCHENSINKA_CHANNEL_A_COMPARATOR_ENABLE = 0x80
KITCHENSINKA_CHANNEL_B_COMPARATOR_ENABLE = 0x40
KITCHENSINKB_ANALOG_FILTER_ENABLE = 0x80
KITCHENSINKB_WAVEFORM_GENERATOR_ENABLE = 0x40
class BufferModes:
Single = 0
Chop = 1
Dual = 2
ChopDual = 3
Macro = 4
MacroChop = 5
class SpockOptions:
TriggerInvert = 0x40
TriggerSourceA = 0x00
TriggerSourceB = 0x04
TriggerSwap = 0x02
TriggerSampledAnalog = 0x00
TriggerHardware = 0x01
class KitchenSinkA:
ChannelAComparatorEnable = 0x80
ChannelBComparatorEnable = 0x40
class KitchenSinkB:
AnalogFilterEnable = 0x80
WaveformGeneratorEnable = 0x40
class VirtualMachine:
class Transaction:
def __init__(self, vm):
self._vm = vm
def append(self, cmd):
self._data += cmd
async def __aenter__(self):
self._data = b''
self._vm._transactions.append(self)
return self
async def __aexit__(self, exc_type, exc_value, traceback):
self._vm._transactions.pop()
if exc_type is None:
await self._vm.issue(self._data)
return False
def __init__(self, stream):
self._stream = stream
@ -219,8 +224,8 @@ class VirtualMachine:
async def set_registers(self, **kwargs):
cmd = ''
r0 = r1 = None
for base, name in sorted((self.Registers[name][0], name) for name in kwargs):
base, dtype, desc = self.Registers[name]
for base, name in sorted((Registers[name][0], name) for name in kwargs):
base, dtype, desc = Registers[name]
for i, byte in enumerate(self.encode(kwargs[name], dtype)):
if cmd:
cmd += 'z'
@ -239,7 +244,7 @@ class VirtualMachine:
await self.issue(cmd + 's')
async def get_register(self, name):
base, dtype, desc = self.Registers[name]
base, dtype, desc = Registers[name]
await self.issue('{:02x}@p'.format(base))
values = []
width = self.calculate_width(dtype)