mirror of
https://github.com/jonathanhogg/scopething
synced 2025-07-14 03:02:09 +01:00
Default to 3.3V logic levels if only capturing logic signals; neaten use of registers in vm
This commit is contained in:
Jonathan Hogg
9
scope.py
9
scope.py
@ -59,6 +59,8 @@ class Scope(vm.VirtualMachine):
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self.analog_default_high = 8
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self.analog_lo_min = 0.07
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self.analog_hi_max = 0.88
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self.logic_low = 0
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self.logic_high = 3.3
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self.capture_clock_period = 25e-9
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self.capture_buffer_size = 12<<10
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self.timeout_clock_period = 6.4e-6
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@ -81,6 +83,7 @@ class Scope(vm.VirtualMachine):
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analog_channels = set()
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logic_channels = set()
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for channel in channels:
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channel = channel.upper()
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if channel in {'A', 'B'}:
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analog_channels.add(channel)
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if trigger is None:
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@ -89,7 +92,7 @@ class Scope(vm.VirtualMachine):
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logic_channels.update(range(8))
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if trigger is None:
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trigger = {0: 1}
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elif channel.startswith('L'):
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elif channel in {'L0', 'L1', 'L2', 'L3', 'L4', 'L5', 'L6', 'L7'}:
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i = int(channel[1:])
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logic_channels.add(i)
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if trigger is None:
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@ -137,11 +140,11 @@ class Scope(vm.VirtualMachine):
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lo, hi = low, high
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else:
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if low is None:
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low = self.analog_default_low
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low = self.analog_default_low if analog_channels else self.logic_low
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elif low < self.analog_default_low:
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Log.warning(f"Voltage range is below safe minimum: {low} < {self.analog_default_low}")
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if high is None:
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high = self.analog_default_high
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high = self.analog_default_high if analog_channels else self.logic_high
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elif high > self.analog_default_high:
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Log.warning(f"Voltage range is above safe maximum: {high} > {self.analog_default_high}")
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lo, hi = self.calculate_lo_hi(low, high)
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238
vm.py
238
vm.py
@ -24,79 +24,120 @@ import struct
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Log = logging.getLogger('vm')
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class Register(namedtuple('Register', ['base', 'dtype', 'description'])):
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def encode(self, value):
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sign = self.dtype[0]
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if '.' in self.dtype:
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whole, fraction = map(int, self.dtype[1:].split('.', 1))
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width = whole + fraction
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value = int(round(value * (1 << fraction)))
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else:
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width = int(self.dtype[1:])
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if sign == 'U':
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n = 1 << width
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value = max(0, min(value, n-1))
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bs = struct.pack('<I', value)
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elif sign == 'S':
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n = 1 << (width - 1)
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value = max(-n, min(value, n-1))
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bs = struct.pack('<i', value)
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else:
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raise TypeError("Unrecognised dtype")
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return bs[:width//8]
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def decode(self, bs):
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if len(bs) < 4:
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bs = bs + bytes(4 - len(bs))
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sign = self.dtype[0]
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if sign == 'U':
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value = struct.unpack('<I', bs)[0]
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elif sign == 'S':
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value = struct.unpack('<i', bs)[0]
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else:
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raise TypeError("Unrecognised dtype")
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if '.' in self.dtype:
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whole, fraction = map(int, self.dtype[1:].split('.', 1))
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value = value / (1 << fraction)
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return value
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def calculate_width(self):
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if '.' in self.dtype:
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return sum(map(int, self.dtype[1:].split('.', 1))) // 8
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else:
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return int(self.dtype[1:]) // 8
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Registers = {
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"TriggerLogic": (0x05, 'U8', "Trigger Logic, one bit per channel (0 => Low, 1 => High)"),
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"TriggerMask": (0x06, 'U8', "Trigger Mask, one bit per channel (0 => Don’t Care, 1 => Active)"),
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"SpockOption": (0x07, 'U8', "Spock Option Register (see bit definition table for details)"),
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"SampleAddress": (0x08, 'U24', "Sample address (write) 24 bit"),
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"SampleCounter": (0x0b, 'U24', "Sample address (read) 24 bit"),
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"TriggerIntro": (0x32, 'U16', "Edge trigger intro filter counter (samples/2)"),
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"TriggerOutro": (0x34, 'U16', "Edge trigger outro filter counter (samples/2)"),
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"TriggerValue": (0x44, 'S0.16', "Digital (comparator) trigger (signed)"),
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"TriggerTime": (0x40, 'U32', "Stopwatch trigger time (ticks)"),
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"ClockTicks": (0x2e, 'U16', "Master Sample (clock) period (ticks)"),
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"ClockScale": (0x14, 'U16', "Clock divide by N (low byte)"),
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"TraceOption": (0x20, 'U8', "Trace Mode Option bits"),
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"TraceMode": (0x21, 'U8', "Trace Mode (see Trace Mode Table)"),
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"TraceIntro": (0x26, 'U16', "Pre-trigger capture count (samples)"),
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"TraceDelay": (0x22, 'U32', "Delay period (uS)"),
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"TraceOutro": (0x2a, 'U16', "Post-trigger capture count (samples)"),
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"Timeout": (0x2c, 'U16', "Auto trace timeout (auto-ticks)"),
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"Prelude": (0x3a, 'U16', "Buffer prefill value"),
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"BufferMode": (0x31, 'U8', "Buffer mode"),
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"DumpMode": (0x1e, 'U8', "Dump mode"),
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"DumpChan": (0x30, 'U8', "Dump (buffer) Channel (0..127,128..254,255)"),
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"DumpSend": (0x18, 'U16', "Dump send (samples)"),
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"DumpSkip": (0x1a, 'U16', "Dump skip (samples)"),
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"DumpCount": (0x1c, 'U16', "Dump size (samples)"),
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"DumpRepeat": (0x16, 'U16', "Dump repeat (iterations)"),
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"StreamIdent": (0x36, 'U8', "Stream data token"),
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"StampIdent": (0x3c, 'U8', "Timestamp token"),
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"AnalogEnable": (0x37, 'U8', "Analog channel enable (bitmap)"),
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"DigitalEnable": (0x38, 'U8', "Digital channel enable (bitmap)"),
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"SnoopEnable": (0x39, 'U8', "Frequency (snoop) channel enable (bitmap)"),
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"Cmd": (0x46, 'U8', "Command Vector"),
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"Mode": (0x47, 'U8', "Operation Mode (per command)"),
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"Option": (0x48, 'U16', "Command Option (bits fields per command)"),
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"Size": (0x4a, 'U16', "Operation (unit/block) size"),
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"Index": (0x4c, 'U16', "Operation index (eg, P Memory Page)"),
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"Address": (0x4e, 'U16', "General purpose address"),
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"Clock": (0x50, 'U16', "Sample (clock) period (ticks)"),
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"Modulo": (0x52, 'U16', "Modulo Size (generic)"),
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"Level": (0x54, 'U0.16', "Output (analog) attenuation (unsigned)"),
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"Offset": (0x56, 'S0.16', "Output (analog) offset (signed)"),
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"Mask": (0x58, 'U16', "Translate source modulo mask"),
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"Ratio": (0x5a, 'U16.16', "Translate command ratio (phase step)"),
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"Mark": (0x5e, 'U16', "Mark count/phase (ticks/step)"),
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"Space": (0x60, 'U16', "Space count/phase (ticks/step)"),
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"Rise": (0x82, 'U16', "Rising edge clock (channel 1) phase (ticks)"),
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"Fall": (0x84, 'U16', "Falling edge clock (channel 1) phase (ticks)"),
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"Control": (0x86, 'U8', "Clock Control Register (channel 1)"),
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"Rise2": (0x88, 'U16', "Rising edge clock (channel 2) phase (ticks)"),
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"Fall2": (0x8a, 'U16', "Falling edge clock (channel 2) phase (ticks)"),
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"Control2": (0x8c, 'U8', "Clock Control Register (channel 2)"),
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"Rise3": (0x8e, 'U16', "Rising edge clock (channel 3) phase (ticks)"),
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"Fall3": (0x90, 'U16', "Falling edge clock (channel 3) phase (ticks)"),
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"Control3": (0x92, 'U8', "Clock Control Register (channel 3)"),
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"EepromData": (0x10, 'U8', "EE Data Register"),
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"EepromAddress": (0x11, 'U8', "EE Address Register"),
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"ConverterLo": (0x64, 'U0.16', "VRB ADC Range Bottom (D Trace Mode)"),
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"ConverterHi": (0x66, 'U0.16', "VRB ADC Range Top (D Trace Mode)"),
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"TriggerLevel": (0x68, 'U0.16', "Trigger Level (comparator, unsigned)"),
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"LogicControl": (0x74, 'U8', "Logic Control"),
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"Rest": (0x78, 'U16', "DAC (rest) level"),
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"KitchenSinkA": (0x7b, 'U8', "Kitchen Sink Register A"),
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"KitchenSinkB": (0x7c, 'U8', "Kitchen Sink Register B"),
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"Map0": (0x94, 'U8', "Peripheral Pin Select Channel 0"),
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"Map1": (0x95, 'U8', "Peripheral Pin Select Channel 1"),
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"Map2": (0x96, 'U8', "Peripheral Pin Select Channel 2"),
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"Map3": (0x97, 'U8', "Peripheral Pin Select Channel 3"),
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"Map4": (0x98, 'U8', "Peripheral Pin Select Channel 4"),
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"Map5": (0x99, 'U8', "Peripheral Pin Select Channel 5"),
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"Map6": (0x9a, 'U8', "Peripheral Pin Select Channel 6"),
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"Map7": (0x9b, 'U8', "Peripheral Pin Select Channel 7"),
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"MasterClockN": (0xf7, 'U8', "PLL prescale (DIV N)"),
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"MasterClockM": (0xf8, 'U16', "PLL multiplier (MUL M)"),
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"TriggerLogic": Register(0x05, 'U8', "Trigger Logic, one bit per channel (0 => Low, 1 => High)"),
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"TriggerMask": Register(0x06, 'U8', "Trigger Mask, one bit per channel (0 => Don’t Care, 1 => Active)"),
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"SpockOption": Register(0x07, 'U8', "Spock Option Register (see bit definition table for details)"),
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"SampleAddress": Register(0x08, 'U24', "Sample address (write) 24 bit"),
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"SampleCounter": Register(0x0b, 'U24', "Sample address (read) 24 bit"),
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"TriggerIntro": Register(0x32, 'U16', "Edge trigger intro filter counter (samples/2)"),
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"TriggerOutro": Register(0x34, 'U16', "Edge trigger outro filter counter (samples/2)"),
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"TriggerValue": Register(0x44, 'S0.16', "Digital (comparator) trigger (signed)"),
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"TriggerTime": Register(0x40, 'U32', "Stopwatch trigger time (ticks)"),
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"ClockTicks": Register(0x2e, 'U16', "Master Sample (clock) period (ticks)"),
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"ClockScale": Register(0x14, 'U16', "Clock divide by N (low byte)"),
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"TraceOption": Register(0x20, 'U8', "Trace Mode Option bits"),
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"TraceMode": Register(0x21, 'U8', "Trace Mode (see Trace Mode Table)"),
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"TraceIntro": Register(0x26, 'U16', "Pre-trigger capture count (samples)"),
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"TraceDelay": Register(0x22, 'U32', "Delay period (uS)"),
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"TraceOutro": Register(0x2a, 'U16', "Post-trigger capture count (samples)"),
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"Timeout": Register(0x2c, 'U16', "Auto trace timeout (auto-ticks)"),
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"Prelude": Register(0x3a, 'U16', "Buffer prefill value"),
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"BufferMode": Register(0x31, 'U8', "Buffer mode"),
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"DumpMode": Register(0x1e, 'U8', "Dump mode"),
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"DumpChan": Register(0x30, 'U8', "Dump (buffer) Channel (0..127,128..254,255)"),
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"DumpSend": Register(0x18, 'U16', "Dump send (samples)"),
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"DumpSkip": Register(0x1a, 'U16', "Dump skip (samples)"),
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"DumpCount": Register(0x1c, 'U16', "Dump size (samples)"),
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"DumpRepeat": Register(0x16, 'U16', "Dump repeat (iterations)"),
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"StreamIdent": Register(0x36, 'U8', "Stream data token"),
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"StampIdent": Register(0x3c, 'U8', "Timestamp token"),
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"AnalogEnable": Register(0x37, 'U8', "Analog channel enable (bitmap)"),
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"DigitalEnable": Register(0x38, 'U8', "Digital channel enable (bitmap)"),
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"SnoopEnable": Register(0x39, 'U8', "Frequency (snoop) channel enable (bitmap)"),
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"Cmd": Register(0x46, 'U8', "Command Vector"),
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"Mode": Register(0x47, 'U8', "Operation Mode (per command)"),
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"Option": Register(0x48, 'U16', "Command Option (bits fields per command)"),
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"Size": Register(0x4a, 'U16', "Operation (unit/block) size"),
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"Index": Register(0x4c, 'U16', "Operation index (eg, P Memory Page)"),
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"Address": Register(0x4e, 'U16', "General purpose address"),
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"Clock": Register(0x50, 'U16', "Sample (clock) period (ticks)"),
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"Modulo": Register(0x52, 'U16', "Modulo Size (generic)"),
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"Level": Register(0x54, 'U0.16', "Output (analog) attenuation (unsigned)"),
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"Offset": Register(0x56, 'S0.16', "Output (analog) offset (signed)"),
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"Mask": Register(0x58, 'U16', "Translate source modulo mask"),
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"Ratio": Register(0x5a, 'U16.16', "Translate command ratio (phase step)"),
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"Mark": Register(0x5e, 'U16', "Mark count/phase (ticks/step)"),
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"Space": Register(0x60, 'U16', "Space count/phase (ticks/step)"),
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"Rise": Register(0x82, 'U16', "Rising edge clock (channel 1) phase (ticks)"),
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"Fall": Register(0x84, 'U16', "Falling edge clock (channel 1) phase (ticks)"),
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"Control": Register(0x86, 'U8', "Clock Control Register (channel 1)"),
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"Rise2": Register(0x88, 'U16', "Rising edge clock (channel 2) phase (ticks)"),
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"Fall2": Register(0x8a, 'U16', "Falling edge clock (channel 2) phase (ticks)"),
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"Control2": Register(0x8c, 'U8', "Clock Control Register (channel 2)"),
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"Rise3": Register(0x8e, 'U16', "Rising edge clock (channel 3) phase (ticks)"),
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"Fall3": Register(0x90, 'U16', "Falling edge clock (channel 3) phase (ticks)"),
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"Control3": Register(0x92, 'U8', "Clock Control Register (channel 3)"),
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"EepromData": Register(0x10, 'U8', "EE Data Register"),
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"EepromAddress": Register(0x11, 'U8', "EE Address Register"),
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"ConverterLo": Register(0x64, 'U0.16', "VRB ADC Range Bottom (D Trace Mode)"),
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"ConverterHi": Register(0x66, 'U0.16', "VRB ADC Range Top (D Trace Mode)"),
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"TriggerLevel": Register(0x68, 'U0.16', "Trigger Level (comparator, unsigned)"),
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"LogicControl": Register(0x74, 'U8', "Logic Control"),
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"Rest": Register(0x78, 'U16', "DAC (rest) level"),
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"KitchenSinkA": Register(0x7b, 'U8', "Kitchen Sink Register A"),
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"KitchenSinkB": Register(0x7c, 'U8', "Kitchen Sink Register B"),
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"Map0": Register(0x94, 'U8', "Peripheral Pin Select Channel 0"),
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"Map1": Register(0x95, 'U8', "Peripheral Pin Select Channel 1"),
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"Map2": Register(0x96, 'U8', "Peripheral Pin Select Channel 2"),
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"Map3": Register(0x97, 'U8', "Peripheral Pin Select Channel 3"),
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"Map4": Register(0x98, 'U8', "Peripheral Pin Select Channel 4"),
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"Map5": Register(0x99, 'U8', "Peripheral Pin Select Channel 5"),
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"Map6": Register(0x9a, 'U8', "Peripheral Pin Select Channel 6"),
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"Map7": Register(0x9b, 'U8', "Peripheral Pin Select Channel 7"),
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"MasterClockN": Register(0xf7, 'U8', "PLL prescale (DIV N)"),
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"MasterClockM": Register(0xf8, 'U16', "PLL multiplier (MUL M)"),
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}
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class TraceMode(IntEnum):
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@ -181,45 +222,6 @@ CaptureModes = [
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CaptureMode( 4, 7, 5, 2, 1, True, False, TraceMode.MixedShotChop, BufferMode.ChopDual),
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]
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def encode(value, dtype):
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sign = dtype[0]
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if '.' in dtype:
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whole, fraction = map(int, dtype[1:].split('.', 1))
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width = whole + fraction
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value = int(round(value * (1 << fraction)))
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else:
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width = int(dtype[1:])
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if sign == 'U':
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n = 1 << width
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value = max(0, min(value, n-1))
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bs = struct.pack('<I', value)
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elif sign == 'S':
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n = 1 << (width - 1)
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value = max(-n, min(value, n-1))
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bs = struct.pack('<i', value)
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else:
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raise TypeError("Unrecognised type")
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return bs[:width//8]
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def decode(bs, dtype):
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if len(bs) < 4:
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bs = bs + bytes(4 - len(bs))
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sign = dtype[0]
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if sign == 'U':
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value = struct.unpack('<I', bs)[0]
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elif sign == 'S':
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value = struct.unpack('<i', bs)[0]
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if '.' in dtype:
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whole, fraction = map(int, dtype[1:].split('.', 1))
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value = value / (1 << fraction)
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return value
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def calculate_width(dtype):
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if '.' in dtype:
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return sum(map(int, dtype[1:].split('.', 1))) // 8
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else:
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return int(dtype[1:]) // 8
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class VirtualMachine:
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@ -301,9 +303,9 @@ class VirtualMachine:
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async def set_registers(self, **kwargs):
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cmd = ''
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r0 = r1 = None
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for base, name in sorted((Registers[name][0], name) for name in kwargs):
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base, dtype, desc = Registers[name]
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bs = encode(kwargs[name], dtype)
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for base, name in sorted((Registers[name].base, name) for name in kwargs):
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register = Registers[name]
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bs = register.encode(kwargs[name])
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Log.debug(f"{name} = 0x{''.join(f'{b:02x}' for b in reversed(bs))}")
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for i, byte in enumerate(bs):
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if cmd:
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@ -323,15 +325,15 @@ class VirtualMachine:
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await self.issue(cmd + 's')
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async def get_register(self, name):
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base, dtype, desc = Registers[name]
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await self.issue(f'{base:02x}@p')
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register = Registers[name]
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await self.issue(f'{register.base:02x}@p')
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values = []
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width = calculate_width(dtype)
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width = register.calculate_width()
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for i in range(width):
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values.append(int((await self.read_replies(2))[1], 16))
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if i < width-1:
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await self.issue(b'np')
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return decode(bytes(values), dtype)
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return register.decode(bytes(values))
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async def issue_get_revision(self):
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await self.issue(b'?')
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